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preliminary i ntegrated c ircuits d ivision ds-cpc7220-r00l preliminary 1 features ? processed with bcdmos on soi (silicon on insulator) ? flexible high voltage supplies up to v pp -v nn =200v ? dc to 10mhz analog signal frequency ? -60db minimum output-off isolation at 5mhz ? low quiescent power dissipation (< 1 ? a typical) ? output on-resistance typically 20 ? ? ttl i/o's for 3.3v interface ? adjustable high voltage supplies ? surface mount package applications ? ultrasound imaging ? printers ? industrial controls and measurement ? piezoelectric transducer drivers figure 1. block diagram description the cpc7220 is a low charge injection 8-channel high-voltage analog switch integrated circuit (ic) for use in applications requiring high voltage switching. control of the high voltage switching is via low voltage ttl logic level compatible inputs for direct connectivity to the system controller. switch manipulation is managed by an 8-bit serial to parallel shift register whose outputs are buffered and stored by an 8-bit transparent latch. level shifters buffer the latch outputs and operate the high voltage switches. because the cpc7220 is capable of switching high load voltages and has a flexible load voltage range, e.g. v pp /v nn : +40v/-160v or +100v/-100v, it is well suited for many medical and industrial applications such as medical ultrasound imaging, printers, and industrial measurement equipment. construction of the high voltage switches using ixys integrated circuits divi sion's reliable bcdmos process technology on soi (silicon on insulator) allow the switches to be organized as solid state switches with direct gate drive. ordering information clk d cl le cl d le cl d le cl d le cl d le cl d le cl d le cl d le sw0 sw1 sw2 sw3 sw4 sw5 sw6 sw7 d i n d out cl le v nn v pp sr0 sr7 sr1 sr2 sr3 sr4 sr5 sr6 ls0 ls7 ls1 ls2 ls3 ls4 ls5 ls6 l0 l7 l1 l2 l3 l4 l5 l6 latches shift register switches le v el shifters part number description cpc7220w 28-lead plcc in tubes (37/tube) cpc7220wtr 28-lead plcc tape & reel (500/reel) CPC7220K 48-lead lqfp in trays (250/tray) CPC7220Ktr 48-lead lqfp tape & reel (2000/reel) e 3 pb cpc7220 low charge injection, 8-channel high voltage analog switch
preliminary i ntegrated c ircuits d ivision cpc7220 2 preliminary r00l 1. specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 package pinout, plcc-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 package pinout, lqfp-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.5 absolute maximum ratings @ 25c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.6 operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.7 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2. functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 logic timing waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3. manufacturing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 moisture sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 esd sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 board wash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.1 cpc7220w 28-pin plcc package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.2 CPC7220K 48-pin lqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6 tape and reel specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6.1 cpc7220wtr plcc-28 tape & reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6.2 CPC7220Ktr lqfp-48 tape & reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
preliminary i ntegrated c ircuits d ivision cpc7220 r00l preliminary 3 1. specifications 1.1 package pinout, plcc-28 1.2 pin description 4 26 25 19 27 2 8 2 3 24 23 22 21 20 12 1 8 17 16 15 14 13 5 11 67 8 910 1 pin name description 1sw3sw3 output 2sw3sw3 output 3sw2sw2 output 4sw2sw2 output 5sw1sw1 output 6sw1sw1 output 7sw0sw0 output 8sw0sw0 output 10 v pp switch positive high voltage supply 12 v nn switch negative high voltage supply 13 gnd ground 14 v dd logic positive voltage supply 16 d in serial data input 17 clk clock input, positive edge trigger 18 le latch enable, active low 19 cl latch clear, active high clears latches and opens switches 20 d out serial data output 21 sw7 sw7 output 22 sw7 sw7 output 23 sw6 sw6 output 24 sw6 sw6 output 25 sw5 sw5 output 26 sw5 sw5 output 27 sw4 sw4 output 28 sw4 sw4 output 9, 11, 15 n/c no connection
preliminary i ntegrated c ircuits d ivision cpc7220 4 preliminary r00l 1.3 package pinout, lqfp-48 1.4 pin description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 pin name description 1sw5sw5 output 3sw4sw4 output 5sw4sw4 output 8sw3sw3 output 10 sw3 sw3 output 12 sw2 sw2 output 14 sw2 sw2 output 16 sw1 sw1 output 18 sw1 sw1 output 20 sw0 sw0 output 22 sw0 sw0 output 24 v pp switch positive high voltage supply 25 v nn switch negative high voltage supply 28 gnd ground 29 v dd logic positive supply voltage 33 d in serial data input 34 clk clock input, positive edge trigger 35 le latch enable, active low 36 cl latch clear, active high clears latches and opens switches 37 d out serial data output 39 sw7 sw7 output 41 sw7 sw7 output 43 sw6 sw6 output 45 sw6 sw6 output 47 sw5 sw5 output 2, 4, 6, 7, 9, 11, 13, 15, 17, 19, 21, 23, 26, 27, 30, 31, 32, 38, 40, 42, 44, 46, 48 n/c no connection
preliminary i ntegrated c ircuits d ivision cpc7220 r00l preliminary 5 1.5 absolute maximum ratings @ 25c absolute maximum ratings are stress ratings. stresses in excess of these ratings can cause permanent damage to the device. functional operati on of the device at conditions beyond those indicated in the op erational sections of this data sheet is not implied. 1.6 operating conditions 1 power up/down sequence is arbitrary except that gnd must be powered-up first and powered-down last. 2 v sig must be v nn ? v sig ? v pp or floating during power up/down transition. 3 rise and fall times of power supplies, v dd , v pp , and v nn , should not be less than 1ms. parameter min max units v dd logic power supply voltage -0.5 6 v v pp - v nn supply voltage -220v v pp positive high voltage supply -0.5 v nn +200 v v nn negative high voltage supply +0.5 v pp -200 v logic input voltages -0.5 v dd +0.3 v analog signal range v nn v pp v peak analog signal current per channel - 1 a power dissipation 28-lead plcc - 2.5 w 48-lead lqfp - 2.3 thermal resistance, junction to ambient 28-lead plcc - 50 ? c/w 48-lead lqfp - 53 storage temperature -60 +150 ? c parameter symbol value logic power supply voltage 1, 3 v dd 4.5v to 6v positive high voltage supply 1, 3 v pp 40v to v nn + 200v negative high voltage supply 1, 3 v nn -40v to -160v analog signal voltage, peak-to-peak 2 v sig v nn +10v to v pp -10v operating temperature t a 0c to 70c
preliminary i ntegrated c ircuits d ivision cpc7220 6 preliminary r00l 1.7 electrical characteristics 1.7.1 switch characteristics (over recomm ended operating conditions unless otherwise noted) parameter symbol test conditions 0c +25c +70c units min max min typ max min max small signal switch on-resistance r ons v pp =40v, v nn =-160v, i sw =5ma - 30 - 20 38 - 48 ? v pp =40v, v nn =-160v, i sw =200ma -25- -27-32 v pp =100v, v nn =-100v, i sw =5ma - 25 - 20 27 - 33 v pp =100v, v nn =-100v, i sw =200ma - 18 - 15 24 - 27 v pp =160v, v nn =-40v, i sw =5ma - 23 - 20 25 - 30 v pp =160v, v nn =-40v, i sw =200ma -22- -25-27 small signal switch on-resistance matching ? r ons i sw =5ma, v pp =100v, v nn =-100v -20- 420-20% large signal switch on-resistance r onl v sig =v pp -10v, i sig =0.8a ---16--- ? switch off leakage per switch i sol v sig =v pp -10v and v nn +10v -5-0.410-15 ? a dc offset, switch off - r l =100k ? - 100 - 0.2 100 - 100 mv dc offset, switch on - r l =100k ? - 100 - 0.2 100 - 100 switch output peak current - v sig duty cycle = 0.1% ----0.8--a output switch frequency f sw duty cycle = 50% ----50--khz maximum v sig slew rate dv/dt v pp =160v, v nn =-40v -20- -20-20v/ns v pp =100v, v nn =-100v v pp =40v, v nn =-160v off isolation k o f=5mhz, 1k ? /15pf load -30 - -30 - - -30 - db f=5mhz, 50 ? load -58 - -58 - - -58 - switch crosstalk k cr f=5mhz, 50 ? load -60 - -60 - - -60 - db output switch isolation diode current i id 300ns pulse width, 2.0% duty cycle - 300 - - 300 - 300 ma off capacitance, sw to gnd c sg(off) v sw =0v, 1mhz 5175 -25520 pf on capacitance, sw to gnd c sg(on) v sw =0v, 1mhz 25 40 20 - 40 25 50 output voltage spike +v spk v pp =40v, v nn =-160v, r l =50 ? --- 37 150 - - mv -v spk 93 +v spk v pp =100v, v nn =-100v, r l =50 ? --- 35 150 - - -v spk 80 +v spk v pp =160v, v nn =-40v, r l =50 ? --- 46 150 - - -v spk 72 charge injection q v pp =100v, v nn =-100v, v sig =0v -880- pc
preliminary i ntegrated c ircuits d ivision cpc7220 r00l preliminary 7 1.7.2 logic dc characteristics (over recomm ended operating conditions unless otherwise noted) 1.7.3 logic timing characteristics (over reco mmended operating conditions unless otherwise noted) parameter symbol test conditions 0c +25c +70c units min max min typ max min max d out source capability v oh i out = - 400 ? a -- v dd -0.7 v dd -0.1 --- v d out sink capability v ol i out = +400 ? a - - - 0.04 0.7 - - logic input capacitance c in - - 10 - - 10 - 10 pf logic input high v ih 4.75v < v dd < 5.25v 2-2--2- v logic input low v il 4.75v < v dd < 5.25v - 0.8 - - 0.8 - 0.8 parameter symbol test conditions 0c +25c 70c units min max min typ max min max setup time before le rises t sd - 150 - 150 - - 150 - ns time width of le t wle - 150 - 150 - - 150 - clock delay time to data out t do - - 150 - 62 150 - 150 time width of cl t wcl - 150 - 150 - - 150 - setup time, data to clock t su - 15 - 15 8 - 20 - hold time, data from clock t h - 35 - 35 - - 35 - clock frequency f clk 50% duty cycle, f data =f clk /2 -5--5-5mhz clock rise and fall times t r , t f - - 50 - - 50 - 50 ns tu r n - o n t i m e t on v sig =v pp -10v, rl=10k ? -5- 2 5-5 ? s turn-off time t off 3
preliminary i ntegrated c ircuits d ivision cpc7220 8 preliminary r00l 1.7.4 supply dc characteristics (over recomm ended operating conditions unless otherwise noted) parameter symbol test conditions 0c +25c +70c units min max min typ max min max v pp quiescent supply current i ppq all switches off ---0.110-- ? a all switches on, i sw =5ma v nn quiescent supply current i nnq all switches off ----0.1-10-- all switches on, i sw =5ma v pp operating supply current i pp v pp =40v, v nn =-160v 50khz output switching frequency with no load -6.5- - 7 - 8 ma v pp =100v, v nn =-100v - 5 - - 5.5 - 5.5 v pp =160v, v nn =-40v -5--5-5.5 v nn operating supply current i nn v pp =40v, v nn =-160v 50khz output switching frequency with no load -6.5- - 7 - 8 ma v pp =100v, v nn =-100v - 5 - - 5.5 - 5.5 v pp =160v, v nn =-40v -5--5-5.5 v dd average supply current i dd f clk =5mhz, v dd =5v -4--4-4ma v dd quiescent supply current i ddq - - 10 - 0.03 10 - 10 ? a
preliminary i ntegrated c ircuits d ivision cpc7220 r00l preliminary 9 2. functional description the cpc7220 takes a serial stream of input data along with a synchronous clock signal. as the clock transits from low to high, the data at the input of each shift register is shifted through from sr(n) to sr(n+1). a high data bit, a "1," represents an on switch; a low data bit, a "0," represents an off switch. data is input and shifted through the internal shift register until all eight shift register positions, sr0 through sr7, are in the desired state. d in : the data-in line presents data bits to be shifted through the internal shift register. clk: the clock signal's risi ng edge is associated only with shifting data into and through the shift register. cl: the clear line overrides all other inputs. w hen cl is high, the shift register is cleared to all 0s and all latches are set low, which causes all output switches to be turned off immediately. w hen cl is low, all output switches remain in whatever state they are in, on or off, in response to clk, latch inputs, and the le signal. le: latch enable controls the state of the latches and thus the state of the eight switches. if le is high, then the latches do not change states, but retain their most recent status: either on or off. w ith le high, input data and clk have no effect on the state of the output switches. if le is low, then all latch outputs and their switch states follow the inputs from the shift register. le is overridden by cl: regardless of le?s state, cl clears the latches. see ?truth table? on page 10 . d out : the data-out pin is the output of sr7. after eight clock pulses, the first bit of eight input data bits is shifted to sr7 and appears on d out . sw0 - sw7: the cpc7220 provides eight high-voltage spst output switches with a typical on-resistance of 20 ? the two connections of each switch are not polarity-sensitive. v pp and v nn : voltage inputs to the level shifters for each switch channel that translate the voltage level of the latch output signals to an appropriate level for the voltages being switched. the high-voltage output switches are turned on and off in response to the data sent into the latches from the shift register: data 0 turns a switch off, data 1 turns a switch on. two or more cpc7220 devices can be cascaded to form an n-switch arrangement. the d out pin of the first is connected to the d in pin of the next in the series. all devices are connected to the same clock (clk) signal. le of all devices would normally be connected, as would cl, but this is not necessary. the first data bit applied to d in of the cpc7220, whether it's a single device or several cascaded devices, ripples through to the last switch output in line after the application of a full clocking sequence of 8 clock pulses per cpc7220. setting the serial i/o device to output the most significant bit (msb) first, results in the msb appearing on s w 7 of the last device in line after a full clocking sequence.. cl d i n clk le sw0 sw7 sw0 sw7 sw0 sw7 d out le cl d i n clk d out le cl d i n clk d out le cl d i n clk cpc7220 cpc7220 cpc7220
preliminary i ntegrated c ircuits d ivision cpc7220 10 preliminary r00l 2.1 truth table notes: 1. the eight s w itches operate independently. 2. serial data is clocked in on the rising edge of the clk signal. 3. the s w itches go to a state retaining their present condition at the rising edge of le. when le is lo w the shift register data flo w s thro u gh the latch. 4. d out is high w hen s w itch 7 is on. 5. shift register clocking has no effect on the s w itch states if le is h. 6. the clear inp u t o v errides all other inp u ts. d0 d1 d2 d3 d4 d5 d6 d7 le cl sw0 sw1 sw2 sw3 sw4 sw5 sw6 sw7 l l l off hll o n l l l off hll o n l l l off hll o n l l l off hll o n l l l off hll o n l l l off hll o n l l l off hll o n l l l off hll o n x x x x x x x x h l hold pre v ious state x x x x x x x x x h off off of f off off off off off
preliminary i ntegrated c ircuits d ivision cpc7220 r00l preliminary 11 2.2 logic timing waveforms d n-1 d n d n+1 50% 50% 50% 50% d in le t wle t sd 50% 50% clk t su t h t do 50% d out t off t on 90% 10% off on cl 50% 50% t wcl v out (typ)
preliminary i ntegrated c ircuits d ivision cpc7220 12 preliminary r00l 3 manufacturing information 3.1 moisture sensitivity all plastic encapsulated semiconductor packages are susc eptible to moisture ingression. ixys integrated circuits division clas sified all of its plastic encapsulated devices for moisture sensitivity according to the latest version of the joint industry standard, ipc/jedec j-std-020 , in force at the time of product evaluation. w e test all of our products to the maximum conditions set forth in the standard, and guarantee proper operation of our devices when handled according to the limitations and information in that standard as well as to any limitations set forth in the information or standards referenced below. failure to adhere to the warnings or limitations as establ ished by the listed specificati ons could result in reduced product performance, reduction of operable life, and/or reduction of overall reliability. this product carries a moisture sensitivity level (msl) rating as shown below, and should be handled according to the requirements of the latest version of the joint industry standard ipc/jedec j-std-033 . 3.2 esd sensitivity this product is esd sensitive , and should be handled according to the industry standard jesd-625 . 3.3 reflow profile this product has a maximum body temperature and time rating as shown below. all other guidelines of j-std-020 must be observed. 3.4 board wash ixys integrated circuits division recommends the use of no-clean flux formulations. however, board washing to remove flux residue is acceptable, and the use of a short drying bake may be necessary. chlorine-based or fluorine-based solvents or fluxes should not be used. clean ing methods that employ ultrasonic energy should not be used. device moisture sensitivity level (msl) rating cpc7220w / CPC7220K msl 1 device maximum temperature x time cpc7220w 245c for 30 seconds CPC7220K 260c for 30 seconds e 3 pb
preliminary i ntegrated c ircuits d ivision cpc7220 r00l preliminary 13 3.5 mechanical dimensions 3.5.1 cpc7220w 28-pin plcc package 3.5.2 CPC7220K 48-pin lqfp package dimensions mm (inches) pcb land pattern 4.3 8 2 0.254 (0.173 0.010) 2.667 0.3 8 1 (0.105 0.015) 0.432 typ (0.017 typ) 0.50 8 mi n (0.020 mi n ) 1.27 typ (0.050 typ) 12.446 0.254 (0.490 0.010) 11.506 0.102 (0.453 0.004) pin 1 designator 11.506 0.102 (0.453 0.004) 12.446 0.254 (0.490 0.010) 11.20 (0.441) 11.20 (0.441) 0.65 (0.026) 2.20 (0.0 8 7) 1.27 (0.050) dimensions mm (inches) 0.60, +0.15/-0.10 (0.024, +0.006/-0.004) 1.60 max (0.063max) 1.40 0.05 (0.055 0.002) 0.05 min / 0.15 max (0.002 min - 0.006 max) 0.50 (0.020) pcb land pattern 8 .40 (0.331) 0.50 (0.020) 0.30 (0.012) 1.50 (0.059) 8 .40 (0.331) pin 4 8 pin 1 0.22 0.05 (0.009 0.002) 7.00 0.10 (0.276 0.004) 9.00 0.20 (0.354 0.00 8 ) 9.00 0.20 (0.354 0.00 8 ) 7.00 0.10 (0.276 0.004)
preliminary i ntegrated c ircuits d ivision cpc7220 14 preliminary r00l 3.6 tape and reel specifications 3.6.1 cpc7220wtr plcc-28 tape & reel 3.6.2 CPC7220Ktr lqfp-48 tape & reel dimensions mm (inches) n ote: unless other w ise noted, tolerance 0.1 (0.004) em b ossment em b ossed carrier top co v er tape thickness 0.102 max. (0.004 max.) 330.2 dia. (13.00 dia.) k 0 =4.9 (0.193) 24.00.3 (0.9450.012) 16.00 (0.63) a 0 =13.0 (0.512) b 0 =13.0 (0.512) dimensions mm (inches) k 0 =2.20 (0.0 8 7) k 1 =1.60 (0.063) 16.00.3 (0.630.012) 12.00 (0.472) a 0 =9.30 (0.366) b 0 =9.30 (0.366) em b ossment em b ossed carrier top co v er tape thickness 0.102 max. (0.004 max.) 330.2 dia. (13.00 dia.) n ote: unless other w ise specified, tolerance 0.1 (0.004) for additional information please visit www.ixysic.com ixys integrated circuits division makes no representations or warranties with respect to the accuracy or completeness of the co ntents of this publication and reserves the right to make changes to sp ecifications and product descriptions at an y time without notice. neither circuit paten t licenses nor indemnity are expressed or implied. except as set forth in ixys integrated circuits div ision?s standard terms and conditions of sale, ixys integrated c ircuits division assumes no liability whatsoever, and disclaims any express or implied warranty, relati ng to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. the products described in this document are not designed, inte nded, authorized or warranted for use as components in systems in tended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of ixys integrated circuits divisi on?s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. ixys integrated circuits division reserves the r ight to discontinue or make changes to its products at any time without notice. specification: ds-cpc7220-r00l ? copyright 2012, ixys integrated circuits division all rights reserved. printed in usa. 12/22/2012

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